Some types of semiconductor memory devices are SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), flash memory, and ferromagnetic RAM. These memory devices can have significantly different operational properties, such as those shown below in Table 1, and accordingly may be appropriate for use in some electronic devices, but not others.
TABLE 1SRAMDRAMFLASHFeRAMMRAMReadHigh speedHalf speedHigh speedHalf speedHalf~High speedWriteHigh speedHalf speedLow speedHalf speedHalf~High speedNon-volatilityNot existNot existExistHalfExistRefreshNot NeededNeededNot NeededNotNot NeededNeededSize of Unit CellLargerSmallerSmallerHalfSmallerLow Voltage for OperationPOSSIBLELIMITEDIMPOSSIBLELIMITEDPOSSIBLE
FIG. 1A is a circuit diagram illustrating a unit cell of a conventional full CMOS SRAM including a P-channel MOSFET used as a pull-up device. Such SRAM devices may provide high speed read and write operations and/or low power consumption. However, as shown in FIG. 1A, the unit cell has six transistors, which may limit the integration density of such unit cells.
FIG. 1B is a circuit diagram of a cell array of a conventional DRAM. The unit cell of the DRAM has one transistor and one capacitor, the DRAM may have a unit cell area of about 10F2, which can be much smaller than the unit cell area of the SRAM (“F” indicates a minimum feature size). Accordingly, the DRAM may have a higher unit cell integration density than the SRAM. In contrast to SRAMs, DRAMs may need a refresh operation every several milliseconds to prevent loss of information due to, for example, leakage of stored charge.
Some electronic devices need non-volatile memory in which stored information is maintained after power to the memory is removed. Flash memories and ferroelectric memories may be used to provide non-volatile memory in such electronic devices.
FIG. 1C is a circuit diagram of a cell array of a conventional NAND flash memory. Because the illustrated NAND flash memory does not include a cell capacitor and a contact in every unit cell, it may have a unit cell area of 4˜8F2, which may be smaller than the unit cell area of a DRAM. Accordingly, NAND flash memory may have a higher integration density than DRAM devices. However, NAND flash memory may need a high driving voltage, such as, for example from 5 to 12 volts in a write mode, and may have a low erase speed. Also, integration density of the NAND flash memory may be reduced by the use of a pumping circuit to elevate the driving voltage. Flash memory may also provide a limited number of rewritable operations, such as, for example 105 to 106 rewrites.
A ferroelectric memory may use, for example, one transistor and one capacitor per unit cell, similar to DRAMs. A ferroelectric memory can be made non-volatile by using a ferroelectric material in the capacitor. Read operations have a destructive affect on information in ferroelectric memory cells, so that a rewrite operation is needed after a read operation. Ferroelectric memories may also provide a limited number of write operations, and may provide relatively average memory access speeds. Ferroelectric memories can be difficult to manufacture because of, for example, reactivity of the ferroelectric materials with hydrogen, high temperatures that may be used for annealing processes, and scalability and cell voltage issues.
Magnetic RAM or Magnetoresistive RAM (MRAM) can be used to provide non-volatile memory that may not be write cycle limited, may allow high integration density, may provide fast memory access operations, and may use a lower voltage relative to ferroelectric memories.
A MRAM includes magnetic tunnel junctions (MTJs) between a digit line and a bit line. The MTJ may include a sequentially stacked structure of a pinning layer, a fixed (pinned) layer, an insulating layer and a free layer. The free layer is connected to the bit line, and the pinning layer is connected to a switch device (i.e., a MOS transistor).
The resistance of a MTJ substantially varies based on the relative magnetization directions of the fixed layer and the free layer (e.g., same or opposite magnetization directions). Consequently, resistivity of the MTJ can be used to indicate information in a MRAM. Generally, the magnetization direction of the fixed layer is not varied during a read/write operation. The magnetization direction of the free layer can be swapped relative to the magnetization direction of the fixed layer. For example, the magnetization direction of the free layer can be the same or the reverse of the fixed layer.
Information may be read from a memory cell by measuring a resistance of the MTJ, and comparing the measured resistance with a reference resistance. A read operation can be classified as an external-reference scheme or as a self-reference scheme based on the selection method of the reference resistance. The external-reference scheme uses resistance of a predetermined external reference device as the reference resistance, and the self-reference scheme (further described below) uses the resistance state of the MTJ itself as the reference resistance.
The resistance of the MTJ can vary exponentially based on the thickness of the insulating layer. For the external reference scheme, variation in the thickness of the insulating layer should be controlled within the small range, such as, for example, about 1 Angstrom, to provide effective reading operations. However, controlling thickness variation to such a small range can be difficult to obtain. Consequently, a self-reference scheme for reading information from a memory cell has drawn increased attention.
FIG. 6 is a flowchart that illustrates operations for reading information from a magnetic memory according to a conventional self-reference scheme.
Referring to FIG. 6, at block 80, an initial electrical resistance value Ri of a MTJ is measured. The initial electric resistance Ri corresponds to initial information recorded in the MTJ. At block 82, a first writing operation writes predetermined information (“final information”) in the MTJ. At block 84, a final electric resistance Rf of the MTJ is measured. At block 86, the initial electric resistance Ri is compared to the final electric resistance Rf. When the initial information in the MTJ is the same as the final information written by the writing operation at block 82, a difference (Rf–Ri) between the initial and final resistances is smaller than a predetermined magnitude. In contrast, when the initial information of the MTJ is different than the final information, the difference (Rf–Ri) between the initial and final resistances is larger than the predetermined magnitude. At block 88, if the initial information is different from final information, a second writing operation is preformed to restore the initial state of the MTJ.
Accordingly, such reading operations using a self-reference scheme are destructive to information in the ferroelectric memory. Destructive reading operations necessitate at least one writing operation for each reading operation.